This invention relates to a synchronizer and a synchronizing method for matching a sync. signal in an input image signal input to a 1-field memory to a reference sync. signal.
Conventionally, there have been two types of synchronizers, one of which is a synchronizer based on a 2-field memory system wherein input image signals are sequentially stored and then output two fields (1 frame) by two fields, the other of which is a synchronizer based on a 1-field memory system wherein image signals are sequentially stored to be output one field by one field. In the synchronizer of the aforesaid 1-field system, sometimes parity of an input side of a 1-field memory may be different from that of an output side (display side) thereof, due to accumulated lag in synchronism between input and output on the basis of aborting or repeatedly reading a specified field of the input image signal. In other words, inversion of scanning lines generated between the input image signals and the output image signals is prevented by delaying a field having become an odd number field anew by 1H (horizontal scanning period) when data from the 1-field memory is read. If inversion occurs, scanning lines of even fields in input image signals and those of odd fields therein are displayed upside down to lose continuity of an original picture. This is very inconvenient. This is due to a NTSC (National Television System Committee) system wherein 1 frame consisting of an odd number of scanning lines (525 lines) is displayed as 2 fields by means of interlace scanning.
A synchronizer of the 1-field memory system detects parity of each field in an input image signal and displays an image signal read from a 1-field memory by 1H (horizontal scan period) according to a result of this detection to prevent inversion of the scanning lines.
That is, as shown in FIG. 1, the conventional synchronizer using a 1-field memory writes an input image signal S.sub.o into the 1-field memory 1 according to a write reset signal RST.sub.W and a system clock 4fsc1 having a frequency of 4 times of a color sub-carrier on the input side, and outputs the written image signal via a parity determination circuit 3 according to a read reset signal RST.sub.R and a system clock 4fsc2 on the output side.
Herein, parity of each field in the input image signal from the aforesaid parity determination circuit 3 is checked, and if parity of a field on the input side does not coincide with that on the output side, the image signal is output through a 1H delay circuit according to a result of this checking.
Thus, in a conventional synchronizer, it is necessary to check whether an odd number field or an even number field of an input image signal should be written, and whether a result of this checking coincide with parity of a field of output signal or not, so that a very complicated system is required to do various types of detection.
In the case of a synchronizer of the 2-field memory system, a required memory capacity is very large, and the price is very expensive. Also in the case of a synchronizer of the 1-field memory system, parity of each field in an input image signal must be checked, so that the system becomes very complicated, and furthermore it is necessary to arrange a parity checking circuit to check coincidence between a result of this detection and parity of each field on the output side (display side).